Double Data Rate, or “DDR” synchronous dynamic random access memories (SDRAMs) are popular due to their performance and density. In order to reduce the amount of real estate on the memory chips, much of the burden of controlling the devices has been offloaded to a memory control device. These memory control devices can reside on microprocessor, application specific integrated circuits (ASIC), field programmable gate array (FPGA) devices or the like, or alternately can reside on devices dedicated solely to the purpose of controlling DDR memories.
In DDR3 and DDR4 applications, the memory control device must insert various types and amounts of delays on the output path with a bit-level granularity. The output delays are required to compensate for various skews present or potentially present within the memory control device, on the printed circuit board (PCB) that connects the memory control device to the SDRAM device(s), on the SDRAM device(s), or a combination thereof. The output delays inserted by the memory control device allow for the interface signals arriving at the SDRAM device(s) to be realigned for proper sampling. The circuitry used to generate and apply the output delays in the memory control device can be complex, encompassing significant integrated circuit (IC) area and can consume significant power.